1) Field of the Invention
This invention relates generally to the fabrication of semiconductor memory devices and more particularly to the fabrication of bit lines over capacitor arrays of memory cells.
2) Description of the Prior Art
The circuit density on a chip has been dramatically increased by very large scale integration (VLSI) semiconductor technologies. The miniaturized devices built in and on semiconductor substrate, making up these circuits, are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device size and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integration, some circuit elements experience electrical limitation due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field-effect-transistor (MOS-FET) and a single capacitor are used extensively in the electronics industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors.
Conventional capacitor DRAM arrays utilize either a buried bit line or a non-buried bit line construction. With buried bit line constructions, bit lines are provided in close vertical proximity to the bit line contacts of the memory cell field effect transistors (FETs), with the cell capacitors being formed horizontally over the top to the word lines and bit lines. With non-buried bit line constructions, deep vertical contacts are made through a thick insulation layer to the cell FETs, with the capacitor constructions being provided over the word lines and beneath the bit lines. Such non-buried bit line constructions are also referred to as "capacitor-under-bit line" or "bit line-over-capacitor" constructions and are the subject of this invention.
The following U.S. patents show related process and bit line structures: U.S. Pat. No. 5,389,566 to Lage, U.S. Pat. No. 5,422,295 to Choi et al. and U.S. Pat. No. 5,401,681 to Dennison. However, the prior art processes can be improved upon by utilizing less photo and etch steps. Many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Other process methods also rely on etching to a predetermined etch depth which can be quite difficult to control in a manufacturing environment. In addition, bit line contact openings often require more process tolerance to prevent the bit line contact from shorting to the word line or the capacitor plate. Moreover, memory cell size must be reduced further to achieve more minimization.
There is a challenge to develop methods of manufacturing these capacitors and bit lines that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and provides maximum process tolerance to maximize product yields.